MCQs Computer Organization and Design 50+

1. Which of the following is correct about Multiplexer

• lt is a data converter
• It can be represented as 4:1 MUX
• Both A and B
• None of the above

Ans: c

2. If the Instruction register IR 7800, AR=123, DR= F800 then the type of instruction will be

• Direct memory reference
• indirect memory reference
• register reference
• Input/output

Ans: c

3. Which of the following forms the part of instruction set completeness

• functional instruction
• control instruction
• transfer instruction
• all of the above

Ans: d

4. Which of the following is incorrect about the control unit

• Control unit can be hardwired or programmed
• Hardwired controls provides faster mode of operation
• programmed controls are dificult to be modify
• Hardwired control used combinational and sequential circuits

Ans: c

5. In a basic computer, the PC is of ____________ bits

• 12
• 8
• 16
• 10

Ans: 16

6. Which of the following is a NOT feature of RISC computers

• Few instructions
• Few addressing modes
• variable length instruction
• hardwired control unit

Ans: c

7. Which of the following is correct about CISC computers

• the instructions acts indirectly on memory address
• machine instructions are designed to match high level language
• both A and B
• none of the above

Ans: c

8. In a basic computer, the machine instruction is executed in following manner

• decode, fetch, execute
• fetch, execute, decode
• fetch, decode, execute
• any of the above sequence

Ans: c

9. To perform a logical AND operation, which of the following symbol is used

• <
• >
• ^
• +

Ans: c

10. Tracks and sectors are associated with

• Magnetic tapes
• Magnetic Drives
• Pen Drives
• All of the above

Ans: b

11. Which of the following is an example of Output device

• Card Puncher
• Card Reader
• Optical Mark Reader
• Bar Code Reader

Ans: a

12. _____________ mapping stores both address and the content of the memory word

• Direct Mapping
• Associative Mapping
• Set associative mapping
• None of the above

Ans: b

13. In a associative Memory, the smallest unit cell C has

• J-K Flip flop
• D flip flop
• S-R flip flop
• T flip flop

Ans: c

14. Data transfer to and from peripheral can be handled using

• Programmed l/O only
• Interrupt-Initiated l/O only
• Direct Memory Access (DMA)
• All of the above

Ans: d

15. Address space and Memory space is associated with which of the memory types

• Cache Memory
• Content Addressable Memory CAM
• Virtual Memory
• Auxiliary Memory

Ans: c

16. Associative mapping procedure is related to

• Cache Memory
• Virtual Memory
• Associative memory
• Auxiliary Memory

Ans: a

17. Memory mapped l/O has

• Increased addressing memory due to the memory mapped l/O
• decreased addressing memory due to the memory mapped l/O
• separate control line
• none of the above

Ans: b

18. Which of the following is/are corect

A) In programmed l/O, CPU stays in a program loop until the l/O unit indicate that it is ready for data transfer

B) The problem mentioned above can be solved by using Interupts

• Only A is correct
• Only B is correct
• Both A and B are correct
• None of them is correct

Ans: c

19. In a associative Memory, the smallest unit cell C has

• J-K Flip flop
• D flip flop
• S-R flip flop
• T flip flop

Ans: c

20. If in a associative memory , Argument register A = 110 111000 and Key register K= 000111000 then the correct content in the match register M from the following will be

• 110 000111
• 101 111011
• 101 110 111
• 111101111

Ans: a

21. Hit Ratio is associated with

• Cache Memory
• Virtual Memory
• Associative Memory
• Main Memory

Ans: a

22. Isolated input-output has

• common address and control bus but separate data bus
• common address and data bus but separate control bus
• common control and data bus but address control bus
• common address, data, and control bus

Ans: b

23. What will the output of the given instruction: ADD R1, R2

• Add the content of R1 and R2 and move the result to RR2
• Add the content of R1 and R2 and move the result to R1
• Add the content of R1 and R2 and move the resultto Accumulator
• None of the above

Ans: b

24. Which of the following is an example of a Peripheral Device

• CPU
• Memory
• Input/Output
• All of the above

Ans: c

25. Input-Output Interface resolves the difference between

• CPU and Memory
• Computer and Peripheral Devices
• Memory and Peripheral Device
• None of the above

Ans: b

26. In programmed /O method,

a) CPU stays in loop until the l/O unit indicated that it is ready for the data transfer

b) It is a time consuming process

• Only A is correct
• Only B is correct
• Both A and B are correct
• None of the above

Ans: c

27. Which of the following statements is/are correct

A) Isolated VO is more efficient than the Memory mapped l/O

B) Memory mapped l/O has increased memory due to addition of l/O

• Only A is correct
• Only B is correct
• Both A and B are correct
• None of the above

Ans: a

28. Which of the following is not an example of shared memory multiprocessor models

• UMA
• NUMA
• PUMA
• COMA

Ans: c

29. In multiprocessor, graceful degradation is

• Ability to continue working even if one processor fail
• Ability to continue working even if Shared Memory fail
• both A and B
• none of the above

Ans: a

30. GPU stands for

• Gradual Processing Unit
• Graphics Processing Unit
• Grand Processing Unit
• None of the above

Ans: b

31. Which of the following is incorrect about GPU

• GPU is similar to CPU
• GPU has large number of cores for faster processing
• GPU has big cache, few threads
• GPU mainly rely on multi-threading

Ans: c

32. Which of the following is not correct about ARM processor

• Low power consumption
• Complex Circuit
• It can’t be used in Windows
• scheduling instructions is difficult

Ans: b

33. Which of the following is not an example of the Physical forms available for interconnection network in a multiprocessor

• Time shared common bus
• Frequency shared common bus
• Cross bar Switch
• Multiport Memory

Ans: b

34. The bus-based multiprocessors are

(a) without cache
(b) with cache
(c) with cache and private memory

• only a and b
• only b & c
• only a and c
• a, b and c are correct

Ans: d

35. Which of the following statements is/are correct

(A) Multiprocessor has separate memory and single CPU
(B) Multiprocessor has shared Memory with multiple CPUs
(C) The CPUs in Multiprocessor can have master-slave relationship only

• Only A is correct
• Only B is correct
• B & C are correct
• A, B are correct

Ans: b

36. Memory Hierarchy in terms of access speed is

• Cache> Main Memory>Register
• Register> Cache> Main Memory
• Register> Main Memory Cache
• Main Memory>Register> Cache

Ans: b

37. Parallel Processing is applicable at

• Job level only
• task level only
• instruction level only
• All of the above

Ans: d

38. Hardware organization of Content Addressable Memory includes

• Argument register only
• Key register
• Match register
• All of the above

Ans: d

39. Which of the following is a replacement algorithm used for page replacement

• Least Recently Used
• Least Recently Utilized
• Least Recurrently Used
• Last Recently Used

Ans: a

40. Which of the following is NOT an example of Input-output command

• Control
• Status
• Data
• all of the above

Ans: b

41. MUX can be used to design

• Adders only
• Fundamental Gates only
• Universal Gates only
• All of the above

Ans: d

42. SR Flip Flop produces invalid output for input

• S=0, R=0
• S=0, R=1
• S=1, R=0
• S=1, R=1

Ans: d

43. Toggle condition in flip flop consider as

• next state same as previous state
• next state delayed version of previous state
• next state shifted version of previous state
• next state is compliment of previous state

Ans: d

44. In programmable logic devices connection are made by means of

• Glue
• Foam
• Fuse
• Wire

Ans: c

45. The difference between half adder and full adder is

• Half adder has two inputs while full adder has three inputs
• Half adder has three inputs while full adder two inputs
• Half adder has two outputs while full adder has tree outputs
• Half adder has three outputs while full adder has two outputs

Ans: a

46. To design a 1024 x 8 RAM using 128 x 8 RAM, how many such chips are required

• 4
• 6
• 8
• 10

Ans: 8

47. Which of the following is a zero address instruction

• LOAD A
• PUSH A
• MOV R1, A
• ADD R1, A

Ans: b

48. In “ARM Processor”, ARM stands for

• Adaptive RISC Machine
• Advanced RISC Machine
• Analytical RISC Machine
• Additional RISC Machine

Ans: b

49. Pipelining increases __ of the processor

• Storage
• Latency
• Predictivity
• Throughput

Ans: d